1. Field of the Invention
The disclosure generally relates to a clock tree circuit, and more particularly, to a clock tree circuit for reducing clock skew and clock jitter.
2. Description of the Related Art
Clock tree circuits are commonly used in the field of digital circuit design. However, since driving paths in clock tree circuits often have different lengths, they tend to result in clock skew and/or clock jitter and degrade the performance of the clock tree circuits. The different lengths of driving paths may also be caused by on-chip variation (OCV), which is unpredictable and uncontrollable. Accordingly, there is a need to design a novel clock tree circuit to solve the above problem.